The handheld consumer products market is aggressive in the miniaturization of portable electronics. Driven at the present time by the cellular phone and digital assistant markets, manufacturers of these devices are challenged by ever shrinking formats and the demand for more PC-like functionality. This challenge asserts pressure on surface mount component manufacturers to design their products to command the smallest area possible. By doing so, this allows portable electronics designers to incorporate additional functions within a device without increasing the overall product size.
In Chip Scale Packaging (CSP) technologies, manufacturers strive to bring the package size as close as possible to the size of the semiconductor chip. The Quad Flat Pack No Lead (QFN) package is an example of a widely accepted and used low cost chip scale package. The QFN platform is cost effective because the platform uses highly automated assembly equipment and molded array package (MAP) encapsulation processes. However, because the QFN is leadless, manufacturers are unable to perform visual inspections of the connections after the QFN devices are attached to next levels of assembly such as printed circuit boards. This can result in end-products having reliability problems. Additionally, existing leaded CSP technologies such as the small outline IC (SOIC) platform are more expensive to manufacture than the QFN platform, and they are not compatible with MAP assembly techniques.
Accordingly, a need exists for a structure and method of manufacturing a leaded package that is cost effective and compatible with MAP assembly techniques.